Programmable integrated circuits (ICs) such as field programmable gate arrays (FPGA) typically include different blocks to accommodate various logic functions and protocols. For instance, programmable ICs may have configurable elements that may be programmed or reprogrammed. These elements may be configured or programmed through configuration random access memory (CRAM) bits, registers, or other memory elements, among others.
However, CRAM bits are typically susceptible to single event upset (SEU) errors. SEU errors are unwanted changes or unwanted effects in IC devices. For example, the state of memory cells or CRAM bits may flip due to radiation or other external causes. Programmable ICs usually have error detection circuitry to detect erroneous settings in the CRAM circuitry that may have been caused by SEU events during configuration. The error detection circuitry usually computes or performs a cyclic redundancy check (CRC) operation on all or a portion of the CRAM circuitry. The CRC may be calculated for each frame of the CRAM array or it may be calculated for all the CRAM bits in the CRAM array.
Generally speaking, programmable ICs, e.g., FPGAs, may be partially reconfigured. In other words, only a portion of the IC's configuration RAM (CRAM) is changed when the IC is reconfigured. The portion of the CRAM that is not reconfigured remains unchanged. This is usually done by performing a logic operation on the existing CRAM values stored in the IC with the reconfiguration CRAM values that are received by the IC to generate a new configuration data. In other words, existing CRAM values stored in the IC are combined with the reconfiguration CRAM values to generate an updated array of CRAM values.
Typically, the new CRC value is calculated dynamically based on the updated CRAM bits. However, if there was a read-back error such that the logic operation to combine the existing CRAM values with the reconfiguration CRAM values was performed using a wrong value of the existing CRAM bits, then the resulting CRAM bits from the logic operation would be incorrect. Likewise, if there was a configuration error, the logic operation would combine the existing CRAM values with the wrong reconfiguration CRAM values and generate incorrect updated CRAM bits.
In these instances, an incorrect CRC value will be calculated because the CRC value is calculated dynamically based on the CRAM bits. The error detection circuitry on the IC that is used to detect erroneous CRAM settings will not be able to detect the error because the generated CRC value matches the incorrect CRAM bits.
As such, it would be desirable to correctly calculate a new CRC value based on the updated CRAM values. It is within this context that the invention arises.